CAMS 2023

As a computer architect, simulators are often our best friend but at the same time, they can be our worst enemy. In this talk, I will present some of the common limitations and challenges of using simulations and how simulations (and modeling) can be your friend. At the same time, I will present steps we should take to ensure simulators do not become our worst enemy. In comparison to simulation data, real systems (and measurements) can provide more realistic data but I will also argue how that can be misleading as well. I will use interconnection network simulations and evaluations as a case study to describe the challenges as well as potential opportunities.

Estimating workload performance for a future processor is a daunting task, as traditional cycle-accurate simulation techniques used by architects are extremely slow. Workload sampling can significantly speed up this process, assuming the regions of interest (ROIs) or the representative sample found can be proven to accurately represent the behavior of the full workload. One standard way to validate the regions of interest is to measure the prediction error, which is the difference in the performance of the full workload and the predicted performance obtained using the representative. Performance is typically obtained using simulation. However, simulation of long-running workloads is infeasible, taking months to years.
In this work, we propose ROIperf, a framework that assesses the quality of workload sampling methodologies based on hardware performance counters by evaluating both the full and representative workloads using real hardware systems. ROIperf allows for the accurate validation of regions of interest by measuring the performance using real hardware instead of simulation. The work aims to present a methodology for long-running programs for which the prevailing simulation-based validation technique is not feasible. We demonstrate the efficacy of ROIperf by evaluating various sample selection methodologies across a wide range of workloads. We evaluate single-threaded and multi-threaded SPEC CPU2017 benchmarks as well as the NAS Parallel Benchmarks to test the proposed technique. ROIperf provides a significant speedup in validating regions selected for simulation, allowing for more widespread use of sample verification, especially for long-running workloads.

The Unlimited Vector Extension (UVE) was already proposed to tackle the limitations of current state-of-the-art Vector-Length Agnostic (VLA) extensions. This is a new Instruction Set Architecture (ISA) extension that aims to reduce loop control and memory access indexation overheads, as well as memory access latency, joining data streaming and Single Instruction, Multiple Data (SIMD) processing. This ISA extension has already been validated in a cycle-accurate simulator, gem5, with a first implementation made on an out-of-order processor model, based on the ARM Cortex-A76. However, as compilation support is currently being developed, and several shortcomings and improvements on the existing specification have been identified, an increasing need to efficiently run and validate UVE code has surged. As such, support for UVE has been added to the Spike simulator. This is the golden reference functional RISC-V ISA simulator, written in C++. To achieve this, the simulator has been extended to accommodate for the necessary architecture changes, such as new registers that hold the data streams (streaming registers) together with a convenient Streaming Unit that emulates the configuration and manipulation of the streams. The result is a powerful tool that provides the possibility to validate all current features and improvements of UVE, along with some preliminary code obtained from the compiler currently under development.

GPU architectures have become popular for executing general-purpose programs. Their many-core architecture supports a large number of threads that run concurrently to hide the latency among dependent instructions. In modern GPU architectures, each SM/core is typically composed of several sub-cores, where each sub-core has its own independent pipeline.
Simulators are a key tool for investigating novel concepts in computer architecture. They must be performance-accurate and have a proper model related to the target hardware to explore the different bottlenecks properly.
This paper presents a wide analysis of different parts of Accel-sim, a popular GPGPU simulator, and some improvements of its model. First, we focus on the front-end and developed a more realistic model. Then, we analyze the way the result bus works and develop a more realistic one. Next, we describe the current memory pipeline model and propose a model for a more cost-effective design. Finally, we discuss other areas of improvement of the simulator.

Computer architecture simulators, one essential tool for chip design concept proving, often provide limited interactivity. These simulations are often seen as black boxes by users, as they usually only display terminal logs during simulation or generate output files after completion. In this paper, we discuss the effective interactivity method in the context of computer hardware design. Particularly, we examine solutions that reveal the execution status and allow users to control the execution of a hardware simulator. To this end, we developed AkitaRTM, an interactive web-based tool for real-time monitoring of hardware simulations. We based the design on observations of inefficiencies in the architect’s workflow when using simulations. We reflected on our design process, particularly on the opportunities for a symbiotic relationship between interface design and its influence on architecture design.

The widespread adoption of hardware cache-partitioning support in commercial processors, especially in the server market, has rekindled interest in research on cache-partitioning policies. Partitioning the Last-Level Cache (LLC), often shared among a number of cores in current multicore processor designs, can help alleviate the negative effects stemming from shared resource contention. Particularly, LLC-partitioning policies significantly influence the degree of throughput and fairness extracted from the system. Unfortunately, recent research on LLC-partitioning systematically employ different sets of metrics, making it difficult to distinguish between the most effective proposals in terms of both throughput and fairness.
This work conducts a simulation-based analysis to shed light on the effect that the choice of different popular metrics for throughput and fairness assessment has on the relative gains associated with LLC-partitioning policies. In light of the results, we also propose a set of recommendations on the utilization and selection criteria for throughput and fairness metrics. Our study reveals that the chosen metric indeed has a profound impact on the reported relative improvement for a partitioning policy, as each metric exhibits a very different improvement range, sometimes even duplicating the percentage increases with respect to other metrics. We find that, putting aside the differences in range, improvements reported by the analyzed throughput metrics show a strong correlation. In contrast, there exists a weaker correlation among many popular fairness metrics regarding their improvement trends.

This paper presents our approach to accelerating computer architecture simulation by leveraging machine learning techniques. Traditional computer architecture simulations are time-consuming, making it challenging to explore different design choices efficiently. Our proposed model utilizes a combination of application features and micro-architectural features to predict the performance of an application. These features are derived from simulations of a small portion of the application. We demonstrate the effectiveness of our approach by building and evaluating a machine learning model that offers significant speedup in architectural exploration. This model demonstrates the ability to predict IPC values for the testing data with a root mean square error of less than 0.1.

Deep Neural Networks (DNNs) have become increasingly capable of tasks ranging from image recognition to human-language generation, predominantly powered by GPUs. With the growing DNNs’ complexity and the datasets’ size, training DNNs with a large number of GPUs is turning into a prevalent strategy. However, when designing and deploying such systems, designers usually rely on testing configurations on hardware, which is both costly and inflexible. While an alternative solution is to test on GPU simulators, they are often too time-consuming. Addressing these challenges, we present TraceSim. TraceSim relies on kernel-level execution traces collected from PyTorch execution and can simulate new hardware configurations with extremely high performance and reasonable accuracy. TraceSim is expected to serve as an essential tool in evaluating the system-level design of large-scale DNN training, especially for massive DNN models.

GPUs have emerged as the dominant architecture for running machine learning applications, while RISC-V has taken the lead in open source hardware and software initiatives. Within our research group, we've introduced an open source project called Vortex, aimed at supporting GPGPU functionality through RISC-V ISA extensions. The Vortex platform offers comprehensive suite of open source tools, including compilers, drivers, and runtime software, all designed to facilitate research in GPU architectures, compilers, and runtime systems. In this presentation, I will present our efforts in modeling both RISC-V GPU software and hardware, and also future directions.